1. Technical Field
The present application relates generally to semiconductor devices and includes methods and structures for improving random single bit (RSB) failure.
2. Related Art
FIG. 1 is a schematic diagram illustrating a cross-sectional view of a memory device 100. The memory device 100 includes substrate 110, oxide-nitride-oxide layer 120, polysilicon layer 130, and hard mask layer 140. For example, the hard mask layer 140 comprises a silicon nitride (Si3N4) layer. The memory device 100 also includes high density plasma (HDP) oxide portions 160. In conventional methods of constructing a memory device 100 may result in various impurities or particles that may lead to RSB failure.
For example, in some conventional memory devices, a particle defect 151 may occur. The particle defect may be a silicon nitride (Si3N4) particle, an impurity particle, or an HDP particle. The particle defect 151 may cause a void or gap 156 at the interface between the HDP oxide portion 160 and polysilicon layer 130, which may result in a path for a later conductive layer to come into contact with the substrate 110. As another example, a polymer residual 152 may result from etching from conventional memory device manufacturing techniques. For example, if an etchant recipe is not optimum, some bi-product residue may form on a side wall of a stack of polysilicon layer 130 and hard mask layer 140, which may also potentially result in a path between a conductive layer and the substrate 110. Weak oxide residues 153 may also exist. For example, if the HDP oxide is not optimum, an interface between the HDP oxide layer 160 and the stacks may be weak, which may also result in a path between a conductive layer and the substrate 110. As another example, phosphoric acid 154 may flow down a crack in the polysilicon layer 130, which can cause chemical damage on the substrate 110 resulting in an increased number of RSB failures. Further, the polysilicon layer 130 may have a rough side wall 155 which may result in cracks between the polysilicon layer 130 and the HDP oxide portions 160, which may also result in an increased number of RSB failures. Any of these failures, if present during the deposition of a conductive layer, may cause the conductive layer to leak down to the substrate, causing a short or a RSB failure.
FIG. 2 is a schematic diagram illustrating transmission electronic microscopy (TEM) view of RSB failures on a wafer 200 for a floating flash gate. As shown in portion 256, a top conductive polysilicon layer PL3 270 has leaked down and is in connection with the substrate 210, which may cause an RSB failure.
Thus, it is desirable to find new approaches for improving memory cell processes, particularly so as to decrease the number of RSB failures in memory devices.